
DS1318
Parallel-Interface Elapsed Time Counter
4
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VALID
DQ0–DQ7
OE
CE
A0–A4
tRC
tAA
tCEA
tCEZ
tOH
tOEZ
tOEL
tCEL
tOEA
Read Cycle Timing
tWC
tWEW
tWEZ
tDS
tDH
tWR
tAS
tAH
DATA INPUT
DQ0–DQ7
WE
CE
A0–A4
DATA OUTPUT
DATA INPUT
VALID
Write Cycle Timing, Write-Enable Controlled
tWC
tDS
tDH
tWR
tAS
tCEW
tAH
DATA INPUT
DQ0–DQ7
WE
CE
A0–A4
DATA INPUT
VALID
Write Cycle Timing, Chip-Enable Controlled